The present invention relates to electronic circuits and more particularly to a circuit arrangement for a capacitive pump.
Capacitive inverters are used to create a negative, i.e. inverted, voltage output in a circuit. Known capacitive inverters are made with two diodes and two capacitors. The arrangement of diodes reduces the output voltage by at least two diode voltage drops. The voltage drops associated with the diodes can be reduced by using Schottky diodes, but even Schottky diodes are susceptible to losses. For example, at xe2x88x9240xc2x0 C., the loss due to each Schottky diode could easily be greater than 0.4V giving a total voltage loss of approximately 0.8V.
The losses associated with the diodes become more of a factor if a low level voltage, e.g. 3.3V or lower, is being inverted.
Accordingly, there remains a need for a capacitive inverter which minimizes losses.
The present invention provides circuitry for a capacitive inverter which produces an output with minimum losses. In another aspect, the capacitive inverter has minimal quiescent current.
In a first aspect, the present invention provides capacitive pump circuit comprising: (a) a buffer having a supply input coupled to a voltage supply rail, an input for receiving a clocking signal and having an output; (b) a level shifter having an input for receiving the clocking signal and an output; (c) an output stage having a first input, a second input, and an output port for outputting a voltage, and an output capacitor, the first input being coupled to the output of the buffer through another capacitor, the second input being coupled to the output of the level shifter; (d) the output stage including first and second transistors connected in a push-pull configuration, the first and second transistors having a control terminal connected to the output of the level shifter, the first transistor having an input terminal connected to a ground rail and an output terminal connected to an input terminal of the second transistor, the connection forming the first input for the output stage, and the second transistor having an output terminal, the output terminal forming the output port, and the output capacitor having one terminal coupled to the output terminal and another terminal coupled to the ground rail.
In another aspect, the present invention provides a voltage doubler circuit comprising: (a) a buffer having a supply input coupled to a voltage supply rail, an input for receiving a clocking signal and having an output; (b) a level shifter having an input for receiving the clocking signal and an output; (c) an output stage having a first input, a second input, and an output port for outputting a voltage, and an output capacitor, the first input being coupled to the output of the buffer through another capacitor, the second input being coupled to the output of the level shifter; (d) the output stage including first and second transistors connected in a push-pull configuration, the first and second transistors each having a control terminal, an input terminal, and an output terminal, the control terminals for the first and said second transistors being connected to the output of the level shifter, the output terminal of the first transistor being connected to one terminal of the output capacitor to form the output port, and the input terminal of the first transistor being connected to the output terminal of the second transistor and one terminal of the capacitor coupled to the output of the buffer, the connection forming the first input for the output stage, and the input terminal of the second transistor being coupled to the other terminal of the output capacitor and the supply voltage rail.